Dept. of Electronics & Communications Engg.
KITS Warangal
Faculty group mail-id : ece@kitsw.ac.in
Faculty Profile
Address/Contact
Office : Staff Room No. 114, Block - VI, Dept. of ECE.
Phone: 0870-2564888(ext:299)
Mobile: 8790657081
Education
B.Tech., E.C.Engg, JNTU, Hyderabad. (2009).
M.Tech., VLSI System Design, JNTU, Hyderabad. (2011).
Ph.D.(Pursuing), Low Power VLSI, JNTU, Hyderabad.
Ch. Pavan kumar
Asst.prof
Electronics & Communication Engg..
Academic Research IDs
Vidwan ID: 176613
SCOPUS ID: 56501390600
Researcher ID: JNE-3721-2023
Google Scholar ID: kefNj_8AAAAJ
ORCID ID: 0000-0001-5421-1434
ACADEMIC AFFILIATION
Details |
FromTo |
Name of the Organization |
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|---|---|---|---|---|
Assistant Professor |
July, 2009 |
June, 2013 |
|
Vaagdevi Engineering College, Warangal. |
Assistant Professor |
June, 2013 |
Till Date |
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Kakatiya Institute of Technology & Science, Warangal. |
RESEARCH INTERESTS
- Low Power Applications,
- Nano Transistors,
- Device Modelling.
PUBLICATIONS
| Publications in Refereed Journals | |
|---|---|
S.No |
Details |
1 |
Ch.Pavan Kumar, Dr.K.Sivani, “Implementation of Efficient Parallel Prefix Adders for Residue Number System” International Journal of Computing and Digital Systems, Int. J. Com. Dig. Sys. 4, No.4 (Oct-2015), ISSN (2210-142X), http://dx.doi.org/10.12785/ijcds/040409. (Scopus). |
2 |
Ch.Pavan Kumar, Dr.K.Sivani, “A Comparative Approach between Conventional Mosfet and Tunnel Field Effect Transistors (Tfets)”, International Journal Of Core Engineering & Management (IJCEM), Special issue ICCEMT-2015(Dec-15), page no.326-335, ISSN: 2348 9510. |
3 |
Ch. Pavan Kumar, Dr. K. Sivani, “Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications” IJCA Proceedings on International Conference on Advances in Emerging Technology ICAET 2017(5):1-5, July 2018, http://www.ijcaonline.org/proceedings/icaet2017/number5/29664-7109 ISBN Number: 973-93-80975-42-7. |
4 |
Ch. Pavan Kumar, Dr. K. Sivani, “A Tunnel Field Effect Transistor Model for Ultra-Low Power Applications” International Journal of Pure and Applied Mathematics, Volume 120,No. 6,2018, 249-260, ISSN: 1314-3395 (Scopus). |
BOOK CHAPTER
S.No |
Details |
1 |
Ch. Pavan Kumar, Dr. K.Sivani, “Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Applications” Lecture Notes in Networks and Systems, Springer Publications, ISSN: 2367-3370,April 2018(Scopus). |
Publications in Refereed Conference Proceedings
S.No |
Details |
1 |
Ch.Pavan Kumar, Dr.K.Sivani, “A Tunnel Field Effect Transistor Model for Ultra-Low Power Applications” International Conference on Innovations & Discoveries in Science, Engineering and Management (ICIDSEM-2018), April 9th & 10th, 2018, Telangana, India. |
2 |
Ch.Pavan Kumar, Dr.K.Sivani, “Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications” 5th International Conference on Advancements in Engineering and Technology (ICAET-2017), March 24-25, 2017, Punjab, India. ISBN Number: 978-81-924893-2-2. |
3 |
Ch.Pavan Kumar, Dr. K.Sivani, “Analyzing the impact of TFETs for ultra-low power design applications.” International Conference on Electrical, Electronics, and Optimization Techniques (IEEE-ICEEOT), March 3-5, 2016. DOI: 10.1109/ICEEOT.2016.7754753 |
4 |
M.devadas, CH.Pavankumar, M. Sanjay and P.srujan “A Novel approach for fault tolerant nano memory applications,” in Proc. Of international conference on nanoscience, engineering & advanced computing (ICNEAC-2011) narsapur, W.G.DIST, Andhra pradesh, 8-10 July, 2011 (ISBN:978-81-8465-683-1) |
5 |
Ch.Pavan Kumar, Dr K.Sivani, “A Tunnel Field Effect transistor is a substitute for ultra-low power applications” International Conference on Advances in Human Machine Interaction (IEEE HMI 2016), March 3-5, 2016 ISBN Number : 978-1-4673-8810-8, DOI: 10.1109/HMI.2016.7449164 |
6 |
Ch. Sravan, CH.Pavankumar, Dr. K. Sivani “A novel approach for power-gating technique with Improved Efficient Charge Recovery Logic” in proc. Of International Conference on Smart Electric Grid (IEEE ISEG), 2014 ,vol., no., pp.1,8, 19-20 Sept. 2014 doi: 10.1109/ISEG.2014.7005583 |
7 |
Ch. Sravan, CH.Pavankumar, Dr. K. Sivani “A Novel Approach for Power Reduction in Asynchronous circuits by using AFPT” in proc. Of Eleventh International Conference on Wireless and Optical Communications Networks (IEEE WOCN), 2014 , vol., no., pp.1,7, 11-13 Sept. 2014,doi: 10.1109/WOCN.2014.6923091 |
PROFESSIONAL AFFILIATION
S.No |
Details |
1 |
Member – Institute of Electrical and Electronics Engineers (IEEE - 92553627) |
2 |
Member – Indian Society for Technical Education (ISTE- LM 74251) |
COURSES TAUGHT
Undergraduate Level |
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|---|---|---|---|---|
Courses Taught |
Currently Teaching |
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Course |
Semester, Year, Branch |
Course |
Semester, Year, Branch |
|
Microprocessor and interfacing |
II Sem, III/IV, IT |
Microprocessor and System Interfacing |
II Sem, III/IV, IT |
|
Microprocessor and Microcontrollers |
II Sem, III/IV, ECE, EEE |
|
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Embedded Systems |
II sem, III/IV, ECE |
|
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VLSI Design and Technology |
II Sem, III/IV, ECE |
|
|
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Electromagnetic Waves and Transmission Lines |
II Sem, III/IV, ECE |
|
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Digital Logic Design & Computer Architecture |
II Sem, III/IV, ECE |
|
|
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Switching Theory and Logic Design |
II Sem, III/IV, ECE |
|
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Computer Architecture |
II Sem, III/IV, ECE |
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Digital Design |
II Sem, III/IV, ECE |
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Post Graduate Level |
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Mixed Signal Design |
II Sem, M.Tech.(VLSI & ES) |
|
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ANN |
I Sem, M.Tech.(DC) |
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FACULTY DEVELOPMENT PROGRAMMES ATTENDED
S. No. |
Programme |
Duration |
Organized by |
1 |
AICTE sponsored Staff Development Program on ‘’Advanced Embedded and Real Time Operating Systems’’ Dept. of ECE, Jayamukhi Institute of Technological Sciences, Narasampet, Warangal, Andhra Pradesh, during 18th June to 1st July 2012. |
18th June to 1st July 2012 |
Jayamukhi Institute of Technological Sciences, Narasampet, Warangal |
2 |
Train the trainer program on analog system design using ASLK starter trainer kit, Organized by CMR Institute of Technology from 23rd to 25th July, 2012, Bangalore |
23rd to 25th July, 2012 |
CMR Institute of Technology |
3 |
3rd Research Methodology Course Organized by Jawaharlal Nehru Technological University Hyderabad, Research and Development Cell ,from 16th to 21st December,2013 at JNTUH Campus. |
16th to 21st December,2013 |
JNTUH |
4 |
INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during May 26-28,2014 |
May 26-28,2014 |
IITBombay |
5 |
INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during November 28-30, 2014. |
November 28-30, 2014. |
IITBombay |
6 |
INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during May 27-29, 2015. |
May 27-29, 2015. |
IITBombay |
7 |
INUP Hands-on Training Workshop on MOSCAP at IIT Bombay during April 18-22, 2016. |
April 18-22, 2016. |
IITBombay |
8 |
INUP Hands-on Training Workshop on MEMs at IIT Bombay during March 20-24, 2017. |
March 20-24, 2017 |
IITBombay |
9 |
IITBombayX: FDP101x Foundation Program in ICT for Education from 03 August to 13th September, 2017. |
03 August to 13th September, 2017. |
|
10 |
IITBombayX: FDP201x Foundation Program in ICT for Education from 3 May to 10 June 2018. |
3 May to 10 June 2018. |
|
11 |
VLSI Design: Bridging Concepts to Practice KITSW One Week 25th -30th March 2019 |
25th -30th March 2019 |
KITSW |
12 |
Trends in Reconfigurable (FPGA) SOC Design E& ICT NITW One Week 25th – 30th November 2018 |
25th – 30th November 2018 |
NITW |
13 |
ET702x: Designing Learner-Centric MOOC IITBX 02nd August 2018 to 06th September 2018. |
02nd August 2018 to 06th September 2018 |
|
14 |
SKVIZ101x: Fundamentals of 3D Visualization IITBX 29th August 2018 to 07th October 2018. |
29th August 2018 to 07th October 2018. |
|
15 |
Deep Learning for engineering applications, Sponsored by DST – ICPS Division Dept. of ECE, KITSW January 06th -08th 2020 |
January 06th -08th 2020 |
KITSW |
16 |
Domain Specific internet of things and illustration of IOTs design using Case Studies, Sponsored by AICTE Dept. of CSE, KITSW January 9th-21 2020 |
January 9th-21 2020 |
KITSW |
AICTE SPONSORED SDP :
participated in the AICTE sponsored Staff Development Program on ‘’Advanced Embedded and Real Time Operating Systems’’ organized by the Dept. of ECE, Jayamukhi Institute of Technological Sciences, Narasampet, Warangal, Andhra Pradesh, during 18th June to 1st July 2012.
PAPERS PRESENTED IN CONFERENCES/SEMINARS/ WORKSHOPS/SYMPOSIA
S. No. |
Title of the Paper presented |
Title of Conference/ Seminar etc. |
Organized by |
1 |
A Tunnel Field Effect Transistor is a Substitute for Ultra-low Power Applications |
International Conference on Advances in Human Machine Interaction (IEEE HMI 2016) |
March 3-5, 2016 ISBN Number : 978-1-4673-8810-8, DOI: 10.1109/HMI.2016.7449164 |
2 |
Analyzing the Impact of TFETs for Ultra-Low Power Design Applications |
International Conference on Electrical, Electronics, and Optimization Techniques (IEEE-ICEEOT), |
March 3-5, 2016.DOI: 10.1109/ICEEOT.2016.7754753 |
BOOKS PUBLISHED
S.No |
Details |
1 |
|
2 |
|
INVITED LECTURES IN CONFERENCE/SEMINAR
S. No. |
Title of Lecture/ Academic Session |
Title of Conference/ Seminar etc. |
Organized by |
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