Dept. of Electronics & Instrumentation Engg.
KITS Warangal
Faculty group mail-id : eie@kitsw.ac.in
Faculty Profile
Address/Contact
Office : Room No. 207, Block - I.
Phone: 0870-2564888(ext:257)
Mobile: 94921174016
E-mail : ksj.eie@kitsw.ac.in
Education
B.Tech., E & I Engg., Kakatiya University, Warangal. (May, 2004).
M.Tech., Embedded Systems, JNTU, Hyderabad. (December, 2012).
Smt. Kotte Shailaja
ASSISTANT PROFESSOR
DEPT. OF ELECTRONICS & INSTRUMENTATION ENGINEERING
Academic Research IDs
Vidwan ID: 179286
SCOPUS ID: 57207487058
Researcher ID: JJE-4657-2023
Google Scholar ID: --
ORCID ID: --
ACADEMIC AFFILIATION
Details |
FromTo |
Name of the Organization |
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|---|---|---|---|---|
Assistant Professor |
February, 2005 |
June, 2007 |
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Vijaya Rural Engineering College, Nizamabad. |
Assistant Professor |
June, 2007 |
December, 2010 |
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Kakatiya Institute of Technology & Science, Warangal |
Assistant Professor |
July, 2011 |
April, 2012 |
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Sumathi Reddy Institute of Technology, Warangal. |
Assistant Professor |
June, 2012 |
Till Date |
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Kakatiya Institute of Technology & Science, Warangal |
PUBLICATIONS
Publications in Refereed Journals |
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S. No |
Details |
1 |
K.Shailaja, P.Anuradha, Syed Mustak Ahmed, K.Sujatha, “An Efficient Implementation of Floating Point Multiplier,” ISSN 0974-2239, Vol. 2, No.3, pp.387-391, 2012. |
2 |
K.Shailaja,S.Prathyusha
“Design of Hybrid Adder using QAC” International Journal of VLSI System Design And Communication Systems ISSN 2322-0929 Vol.02, Issue.07, October-2014, Pages:0593-0596. |
3 |
Kotte, S., & Dabbakuti, J. K., Methods for removal of artifacts from EEG signal: A review. In Journal of Physics: Conference Series (Vol. 1706, No. 1, p. 012093). IOP Publishing. (2020, December). |
4 |
K.Shailaja “Efficient Multiplier design using adaptive hold logic to reduce aging effects”, International Journal of Engineering Technology Science and Research [IJETSR-2017], ISSN 2394-3386, Vol. 04, Issue 11, Pg. 1271-1291, 2017. |
Publications in Refereed Conference Proceedings
S.No |
Details |
1 |
K.Shailaja, P.Anuradha, Syed Mustak Ahmed, K.Sujatha, “An Efficient Implementation of Floating Point Multiplier”, ISSN 0974-2239, Vol. 2, No.3, pp.387-391, 2012. |
2 |
Kotte, S., & Dabbakuti, J. K. (2020, December). Methods for removal of artifacts from EEG signal: A review. International of conference on Advances in Physics and material science:ICAPSM 2020, August-2020 |
PROFESSIONAL AFFILIATION
S.No |
Details |
1 |
Member – Indian Society for Technical Education (ISTE- LM 88307) |
COURSES TAUGHT
Undergraduate Level |
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Courses Taught |
Currently Teaching |
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Course |
Semester, Year, Branch |
Course |
Semester, Year, Branch |
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PC Based Instrumentation |
I Sem, IV/IV EIE |
Analytical Instrumentation |
I Sem, IV/IV, EIE |
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Embedded Systems |
II Sem, IV/IV EIE |
Electronics Measuring Instruments |
V Sem, III, ECE |
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Computer Organization |
II Sem, III/IV, CSE |
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Bio-Medical Instrumentation |
II Sem, III/IV, EIE |
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Digital Electronics |
I Sem, III/IV, CSE |
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Computer Architecture |
I Sem, III/IV, EIE |
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Microprocessor & Interfacing |
II Sem, III/IV, CSE |
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VLSI Design |
II Sem, III/IV, CSE |
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Electronic Equipment Design |
I Sem, II/IV, EIE |
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Electrical Technology |
II Sem, II/IV, ECE |
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Electrical and Electronic Measurements |
I Sem, II/IV, ECE |
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Electrical & Electronic Engineering |
I Sem, II/IV, ME |
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Basic Electronics |
II Sem, II/IV |
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Analytical Instrumentation |
I Sem, IV/IV, EIE |
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Postgraduate Level |
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Embedded System Design |
I Sem, I- VLSI & ES |
RTOS For Embedded Systems |
II Sem,I-VLSI &ES |
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CPLD &FPGA Architectures and Applications |
II Sem, I-VLSI & ES |
Embedded Systems Lab |
II Sem,I –VLSI & ES |
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RTOS For Embedded Systems |
II Sem, I-VLSI & ES |
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Embedded Systems Lab |
II Sem, I –VLSI & ES |
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Microprocessors and Microcontrollers |
II Sem, I –PE |
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WORKSHOPS / STTPs / FDPs ATTENDED
S.No |
Details |
1 |
AICTE Sponsored Two Week Faculty Development Programme (FDP) on “Hands on ProjectBased Approach for Biomedical Signal Analysis using MATLAB” (Phase-1 Online) organized by Department of Electronics and Communication Engineering at Kakatiya Institute of Technology & Science, Warangal, Telangana during 28.12.2020-10.01.2021 |
2 |
AICTE sponsored One week online STTP “Innovative teaching and learning methods for inspiring students”,ITLMIS _Nov 2020,organized by dept.ECE Sagi Rama Krishnam Raju College of Engineering,Bheemvaram 16-20 Nov 2020 |
3 |
One week International FDP on “MEMS based on sensors and actuators for biomedical applications” ,organized by Microelectronics research group,Dept of ECE,KL deemed University |
4 |
Three day STTP on “Artificial Intelligence healthcare sector” conducted by dept.of Biomedical Engineering and IQAC cell. Karpaga Vinayaga College of Engineering and Technology |
5 |
AICTE sponsored Two-week FDP on ‘Bio Medical Signal Processing and Applications” organized by ECE Dept. Sir C.R Reddy College of Engineering. Eluru. Andhra Pradesh (Nov 1st to 14th 2019) |
6 |
DST-ICPS DIVISION Sponsored 3-day National Level Seminar on ‘Deep Learning for Engineering Applications” organized by ECE Dept. KITS Warangal-(Jan 6th -8th 2020) |
7 |
One Week FDP on “VLSI Design: Bridging Concepts to Practice” organized by EIE Dept. KITS-Warangal (March 25th-29th 2019) |
8 |
DST- SERB sponsored One week FDP on “Emerging Trends in Wireless Networks” organized by IT Department (21 - 25 May 2018) |
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